deb_control_files:
- control
- md5sums
deb_fields:
Architecture: amd64
Depends: tcl-dev, libffi-dev, libreadline-dev
Description: |-
Framework for Verilog RTL synthesis (development files)
Yosys is a framework for Verilog RTL synthesis. It currently has extensive
Verilog-2005 support and provides a basic set of synthesis algorithms for
various application domains.
.
Yosys can be adapted to perform any synthesis job by combining the existing
passes (algorithms) using synthesis scripts and adding additional passes as
needed by extending the yosys C++ code base.
.
This package contains the headers and programs needed to build yosys plugins.
Homepage: https://github.com/YosysHQ/yosys
Installed-Size: '475'
Maintainer: Debian Science Maintainers <debian-science-maintainers@lists.alioth.debian.org>
Package: yosys-dev
Priority: optional
Section: electronics
Source: yosys
Version: 0.23-6
srcpkg_name: yosys
srcpkg_version: 0.23-6