deb_control_files:
- control
- md5sums
deb_fields:
Architecture: arm64
Breaks: yosys (<< 0.32-1)
Depends: libbz2-1.0, libc6 (>= 2.38), libgcc-s1 (>= 3.3.1), libreadline8t64 (>=
6.0), libstdc++6 (>= 13.1), zlib1g (>= 1:1.1.4)
Description: |-
Sequential Logic Synthesis and Verification Algorithms
ABC is a system for synthesis and verification of binary sequential logic
circuits appearing in synchronous hardware designs. It combines scalable
logic optimization based on And-Inverter Graphs (AIGs), optimal-delay
DAG-based technology mapping for look-up tables and standard cells, and
innovative algorithms for sequential synthesis and verification.
.
This is a fork of berkeley-abc maintained by the YosysHQ team for use in
the yosys RTL synthesis framework.
Homepage: https://github.com/YosysHQ/yosys
Installed-Size: '14569'
Maintainer: Debian Science Maintainers <debian-science-maintainers@lists.alioth.debian.org>
Package: yosys-abc
Priority: optional
Replaces: yosys (<< 0.32-1)
Section: electronics
Source: yosys (0.33-5)
Version: 0.33-5+b3
srcpkg_name: yosys
srcpkg_version: 0.33-5