37extern unsigned char T_IER;
40extern volatile unsigned char T_CSR;
43extern volatile unsigned T_CNT;
53extern unsigned char T_CR;
56extern unsigned char T_OCR;
60extern volatile unsigned T_ICRA;
63extern volatile unsigned T_ICRB;
66extern volatile unsigned T_ICRC;
69extern volatile unsigned T_ICRD;
74#define TIER_ENABLE_ICA 0x80
75#define TIER_ENABLE_ICB 0x40
76#define TIER_ENABLE_ICC 0x20
77#define TIER_ENABLE_ICD 0x10
78#define TIER_ENABLE_OCA 0x08
79#define TIER_ENABLE_OCB 0x04
80#define TIER_ENABLE_OF 0x02
81#define TIER_RESERVED 0x01
93#define TCSR_RESET_ON_A 0x01
98#define TCR_A_RISING 0x80
99#define TCR_B_RISING 0x40
100#define TCR_C_RISING 0x20
101#define TCR_D_RISING 0x10
102#define TCR_BUFFER_A 0x08
103#define TCR_BUFFER_B 0x04
104#define TCR_CLOCK_2 0x00
105#define TCR_CLOCK_8 0x01
106#define TCR_CLOCK_32 0x02
107#define TCR_CLOCK_EXT 0x03
112#define TOCR_OCRA 0x00
113#define TOCR_OCRB 0x10
114#define TOCR_ENABLE_A 0x08
115#define TOCR_ENABLE_B 0x04
116#define TOCR_HIGH_LEVEL_A 0x02
117#define TOCR_HIGH_LEVEL_B 0x01
125extern unsigned char STCR;
128extern unsigned char T0_CR;
131extern volatile unsigned char T0_CSR;
140extern volatile unsigned char T0_CNT;
144extern unsigned char T1_CR;
147extern volatile unsigned char T1_CSR;
156extern volatile unsigned char T1_CNT;
162#define CR_ENABLE_IRQA 0x40
163#define CR_ENABLE_IRQB 0x80
164#define CR_ENABLE_IRQO 0x20
166#define CR_CLEAR_NEVER 0x00
167#define CR_CLEAR_ON_A 0x08
168#define CR_CLEAR_ON_B 0x10
169#define CR_CLEAR_ON_EXTERN 0x18
178#define CSR_MATCH_A 0x40
179#define CSR_MATCH_B 0x80
180#define CSR_OVERFLOW 0x20
182#define CSR_IGNORE_B 0x00
183#define CSR_0_ON_B 0x04
184#define CSR_1_ON_B 0x08
185#define CSR_TOGGLE_ON_B 0x0c
187#define CSR_IGNORE_A 0x00
188#define CSR_0_ON_A 0x01
189#define CSR_1_ON_A 0x02
190#define CSR_TOGGLE_ON_A 0x03
197extern volatile unsigned char S_RDR;
200extern unsigned char S_TDR;
203extern unsigned char S_MR;
206extern unsigned char S_CR;
209extern volatile unsigned char S_SR;
212extern unsigned char S_BRR;
215extern unsigned char S_TCR;
221#define SMR_ASYNC 0x00
224#define SMR_P_NONE 0x00
225#define SMR_P_EVEN 0x20
226#define SMR_P_ODD 0x30
227#define SMR_1STOP 0x00
228#define SMR_2STOP 0x08
231#define SMR_CLOCK 0x00
232#define SMR_CLOCK_4 0x01
233#define SMR_CLOCK_16 0x02
234#define SMR_CLOCK_64 0x03
237#define SCR_TX_IRQ 0x80
238#define SCR_RX_IRQ 0x40
239#define SCR_TRANSMIT 0x20
240#define SCR_RECEIVE 0x10
241#define SCR_MP_IRQ 0x08
242#define SCR_TE_IRQ 0x04
243#define SCR_INT_CLOCK 0x00
244#define SCR_EXT_CLOCK 0x02
245#define SCR_CLOCK_OUT 0x01
248#define SSR_TRANS_EMPTY 0x80
249#define SSR_RECV_FULL 0x40
250#define SSR_OVERRUN_ERR 0x20
251#define SSR_FRAMING_ERR 0x10
252#define SSR_PARITY_ERR 0x08
253#define SSR_ERRORS 0x38
254#define SSR_TRANS_END 0x04
256#define SSR_MP_TRANSFER 0x01
276extern volatile unsigned char AD_A_H;
280extern volatile unsigned char AD_A_L;
283extern volatile unsigned char AD_B_H;
287extern volatile unsigned char AD_B_L;
290extern volatile unsigned char AD_C_H;
294extern volatile unsigned char AD_C_L;
297extern volatile unsigned char AD_D_H;
301extern volatile unsigned char AD_D_L;
306extern volatile unsigned AD_A;
310extern volatile unsigned AD_B;
314extern volatile unsigned AD_C;
318extern volatile unsigned AD_D;
322extern volatile unsigned char AD_CSR;
325extern unsigned char AD_CR;
332#define ADCSR_END 0x80
333#define ADCSR_ENABLE_IRQ 0x40
334#define ADCSR_START 0x20
335#define ADCSR_SCAN 0x10
336#define ADCSR_TIME_266 0x00
337#define ADCSR_TIME_134 0x08
339#define ADCSR_GROUP_0 0x00
340#define ADCSR_GROUP_1 0x04
342#define ADCSR_AN_0 0x00
343#define ADCSR_AN_1 0x01
344#define ADCSR_AN_2 0x02
345#define ADCSR_AN_3 0x03
351#define ADCR_EXTERN 0x80
359extern unsigned char SYSCR;
361#define SYSCR_SOFTWARE_STANDBY 0x80
382extern volatile unsigned char PORT1;
389extern volatile unsigned char PORT2;
396extern volatile unsigned char PORT3;
403extern volatile unsigned char PORT4;
410extern volatile unsigned char PORT5;
417extern volatile unsigned char PORT6;
421extern volatile unsigned char PORT7;
426extern volatile unsigned int WDT_CSR;
428#define WDT_CSR_PASSWORD (0xA500)
429#define WDT_CSR_ENABLE (0x0020)
430#define WDT_CSR_MODE_WATCHDOG (0x0040)
431#define WDT_CSR_MODE_OVERFLOW (0x0000)
432#define WDT_CSR_WATCHDOG_NMI (0x0000)
433#define WDT_CSR_WATCHDOG_RES (0x0008)
434#define WDT_CSR_CLOCK_2 (0x0000)
435#define WDT_CSR_CLOCK_32 (0x0001)
436#define WDT_CSR_CLOCK_64 (0x0002)
437#define WDT_CSR_CLOCK_128 (0x0003)
438#define WDT_CSR_CLOCK_256 (0x0004)
439#define WDT_CSR_CLOCK_512 (0x0005)
440#define WDT_CSR_CLOCK_2048 (0x0006)
441#define WDT_CSR_CLOCK_4096 (0x0007)
444extern volatile unsigned char WDT_CNT;
446#define WDT_CNT_PASSWORD (0x5A00)
447#define WDT_CNT_CLEAR (0x0000)
448#define WDT_CNT_MSEC_64 (0x0006)
unsigned char T1_CORB
timer 1 constant B register
unsigned char T1_CORA
timer 1 constant A register
unsigned char PORT4_DDR
port 4 data direction register
volatile unsigned char T_CSR
16-bit timer control / status register
volatile unsigned char T0_CNT
timer 0 counter register
volatile unsigned char PORT7
port 7 input register
volatile unsigned char AD_B_L
A/D converter data register B low.
unsigned T_OCRB
16-bit timer output compare register B
volatile unsigned char WDT_CNT
watch dog timer counter register
volatile unsigned char AD_A_L
A/D converter data register A low.
unsigned char PORT6_DDR
port 6 data direction register
unsigned char S_TCR
serial / timer control register
volatile unsigned T_ICRD
16-bit timer input capture D register
unsigned char PORT3_DDR
port 3 data direction register
unsigned char T_CR
16-bit timer control register
unsigned char T_IER
16-bit timer interrupt enable register
volatile unsigned T_ICRA
16-bit timer input capture A register
volatile unsigned char AD_D_H
A/D converter data register D high.
volatile unsigned char AD_A_H
A/D converter data register A high.
volatile unsigned int WDT_CSR
watch dog timer control register
unsigned char PORT3_PCR
port 3 input pull-up control register
unsigned char PORT1_PCR
port 1 input pull-up control register
volatile unsigned char AD_C_L
A/D converter data register C low.
volatile unsigned T_ICRB
16-bit timer input capture B register
unsigned char S_TDR
serial transmit data register
volatile unsigned AD_A
A/D converter data register A.
volatile unsigned char AD_CSR
A/D converter control / status register.
unsigned char STCR
serial / timer control register
volatile unsigned char AD_D_L
A/D converter data register D low.
unsigned char S_BRR
serial baud rate register
unsigned char PORT2_DDR
port 2 data direction register
unsigned char PORT1_DDR
port 1 data direction register
volatile unsigned char T0_CSR
timer 0 control / status register
volatile unsigned char T1_CNT
timer 1 counter register
unsigned char PORT5_DDR
port 5 data direction register
unsigned char T0_CORA
timer 0 constant A register
volatile unsigned T_CNT
16-bit timer count register
unsigned char S_CR
serial control register
unsigned char PORT2_PCR
port 2 input pull-up control register
unsigned char AD_CR
A/D converter control register.
volatile unsigned char PORT3
port 3 I/O register
volatile unsigned char T1_CSR
timer 1 control / status register
volatile unsigned T_ICRC
16-bit timer input capture C register
unsigned char T0_CR
timer 0 control register
unsigned char SYSCR
system control register
unsigned T_OCRA
16-bit timer output compare register A
volatile unsigned char S_RDR
serial receive data register
volatile unsigned char PORT1
port 1 I/O register
unsigned char T1_CR
timer 1 control register
volatile unsigned AD_B
A/D converter data register B.
volatile unsigned char AD_B_H
A/D converter data register B high.
volatile unsigned char PORT2
port 2 I/O register
volatile unsigned AD_D
A/D converter data register D.
volatile unsigned char S_SR
serial status register
unsigned char S_MR
serial mode register
volatile unsigned char AD_C_H
A/D converter data register C high.
unsigned char T0_CORB
timer 0 constant B register
volatile unsigned char PORT6
port 6 I/O register
volatile unsigned AD_C
A/D converter data register C.
volatile unsigned char PORT5
port 5 I/O register
unsigned char T_OCR
16-bit timer output control register
volatile unsigned char PORT4
port 4 I/O register