deb_control_files:
- control
- md5sums
- postinst
- prerm
deb_fields:
Architecture: amd64
Depends: libc6 (>= 2.35), libffi8 (>= 3.4), libgcc-s1 (>= 3.0), libreadline8 (>=
6.0), libstdc++6 (>= 11), libtcl8.6 (>= 8.6.0), zlib1g (>= 1:1.2.0), python3:any,
python3-click, berkeley-abc (>= 1.01+20221019git70cb339+dfsg-3), xdot
Description: |-
Framework for Verilog RTL synthesis
This is a framework for Verilog RTL synthesis. It currently has extensive
Verilog-2005 support and provides a basic set of synthesis algorithms for
various application domains.
.
Yosys can be adapted to perform any synthesis job by combining the existing
passes (algorithms) using synthesis scripts and adding additional passes as
needed by extending the yosys C++ code base.
Homepage: https://github.com/YosysHQ/yosys
Installed-Size: '13599'
Maintainer: Debian Science Maintainers <debian-science-maintainers@lists.alioth.debian.org>
Package: yosys
Priority: optional
Section: electronics
Version: 0.23-6
srcpkg_name: yosys
srcpkg_version: 0.23-6